An efficient implementation of Boolean functions and finite state machines as self-time circuits

General synthesis methods for efficiently implementing self-timed combinational logic (CL) and finite-state machines (FSM) are presented. The resulting CL is shown to require fewer gates than other proposed methods. The FSM is implemented by interconnecting a CL module with a self-time master-slave regime. Alternate FSM synthesis methods are also considered. A formal system of behavioral sequential constraints is presented for each of the systems and their behavior is proven correct. Thus, the synthesized CLs and FSMs can serve as correct-by-construction building blocks for self-timed silicon system compilation.<
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