A 5 ns 1 Mb ECL BiCMOS SRAM

A 1 M-word*1-b emitter-coupled-logic (ECL) SRAM in 0.8- mu m BiCMOS technology that achieves 5-ns access time using (1) wired-OR predecoders, (2) ECL CMOS level converters with partial address decoding, and (3) sensing with small differential voltage swing on long read bus lines is described. The memory cell array is divided into two 512 K-cell subarrays. Each subarray consists of 16 32-kb arrays, each of which is organized into 256 rows and 128 columns. An X-decoder is located between a pair of 32-kb arrays. Address input signals are received by an ECL address buffer. The first circuit for address decoding is a wired-OR predecoder, which does the predecoding and predecoded signal line driving. Predecoded address signals with about 1.2-V voltage swing drive 16.5-mm predecoded lines between two 512-kb subarrays and are received by partial-decoding level converters at corresponding 32-kb arrays.<
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