A Digital 60 Channel Transmultiplexer: Algorithm Minimizing Multiplication Rate and Hardware Implementation

A TDM/FDM conversion algorithm for realizing transmultiplexers with an FFT processor and a set of digital subfilters is proposed which provides a significant saving in multiplication rate. In the proposed algorithm in which an FDM signal is directly sampled, the dimension of the FFT processor is reduced by provision of pre- and postprocessing and the multiplication rate in radix-3 is reduced by refinement of the processing. In addition, the multiplication rate in the subfilters is reduced by the adoption of symmetrical coefficients. Although the direct sampling of an FDM signal has been considered to increase the multiplication rate compared with the sampling with frequency shift of FDM signal. The authors' estimation shows that the increase of multiplication rate in the proposed algorithm keeps within 20 percent compared with that in a typical algorithm based on sampling with frequency shift of FDM signal. Furthermore, it shows that the proposed algorithm reduces the multiplication rate by 30 percent compared with a previously proposed algorithm based on direct sampling of FDM signal. Based on the proposed algorithm, a digital 60 channel transmultiplexer has been implemented. System configuration of the developed equipment is outlined and its measured performance is described.