Static Design of Transistor Diode Logic

Two techniques for static design of drift-tolerant transistor diode logic are described. As the approaches are applicable to other design problems, the descriptions have been given a rather general form. First, three kinds of drift-tolerant design criteria are discussed: worst-case, statistical design, and multiple worst-case. The criteria illustrate different ways in which the information from the specification sheets may be applied to the design inequalities. Second, the form of the design inequalities is discussed. Substantial simplicity is obtained by giving the inequalities a determinant form. Finally, two ways of solving the design inequalities are demonstrated. Both methods will give the results in terms of available resistor values. The
\lambda_s
-method will give the set of highest resistor values which satisfies the design inequalities. The useful region method will determine a family of curves, each curve corresponding to a possible load on the circuit. The region which is limited by a curve illustrates all solutions (or all interesting solutions) to the design problem. The method will enable the designer to take into account the unavoidable correlations between the component parameters due to age, temperature, etc. Due to its nature, one such diagram will, in general, suffice for a project. A diagram which illustrates all possible resistor combinations with which a NAND circuit can drive a given load, is derived in Appendix I. The AND or OR load in question determines which member of the family of curves is applicable. The design of an iterative NOR circuit with minimum power dissipation is described in Appendix II.