Impurity diffusion behavior of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5- mu m Bi-CMOS process

A low-temperature-processed (800-850 degrees C) bipolar transistor design suitable for the high-performance 0.5- mu m BiCMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in the low-concentration base region. and insufficient arsenic diffusion from the poly Si are serious considerations if low-temperature furnace annealing is used. If high-temperature rapid thermal annealing (RTA) is used instead of low-temperature furnace annealing, these problems are resolved. Through impurity diffusion behavior and related electrical bipolar transistor design in the high-performance 0. 5- mu m Bi-CMOS process are proposed. The As-P emitter and selectively implanted collector structures, annealed using RTA, were found to be suitable for the advanced Bi-CMOS process.<
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