Modeling of power supply noise in large chips with nonlinear circuits

In this paper, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. This model was verified by comparing it with SPICE, followed by a large network simulation with both linear and nonlinear circuits. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers and rise time have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise.