A 50-ps 7 K-gate masterslice using mixed cells consisting of an NTL gate and an LCML macrocell

A 7 K-gate bipolar masterslice providing high-speed gates as well as highly functional cells has been developed. A basic mixed cell consisting of both a nonthreshold logic (NTL) gate and an LCML macrocell is introduced. A 1-/spl mu/m-rule super self-aligned process technology (SST-1A) is adopted in combination with three-level metallization technology. A basic NTL gate delay of 50 ps has been achieved with a power dissipation of 1.84 mW. For flip-flop (FF) performance using a macrocell, a toggle frequency of up to 2.6 GHz is obtained with 3.78 mW/FF. For application, a 24-bit parallel multiplier having a multiplication time of 12.8 ns is customized with a power dissipation of 5.1 W.