A 1.5-Mbit/s/spl times/128-channel time-switch LSI for digital still picture exchanges

A high-speed time-switch LSI comprising a major part of a 1.5-Mb/s 128-channel digital still-picture switching system has been developed. A pipelined multiplexer architecture which combines a pipelined multiplexer with a shift register is proposed. This design is suitable for high-speed operation, since it consists of repetitive-element circuits with minimum fan-in and fan-out counts. Using conventional 2.5-/spl mu/m CMOS process technology, the measured maximum clock rate and throughput of a time-switch LSI using this architecture are 56 MHz and 224 Mb/s, respectively, under typical conditions. The throughput is about five times as large as that of a standard-type time-switch LSI that uses a RAM fabricated with 2.2-/spl mu/m NMOS process technology.