A 1-Mbit CMOS dynamic RAM with design-for test functions

A 1-Mb CMOS DRAM measuring 4.3/spl times/11.7 mm/SUP 2/ (50.32 mm/SUP 2/) has been fabricated using 1.0-/spl mu/m CMOS double-poly single-metal process technology. Both moat and second-level poly are clad to reduce circuit propagation delays. The chip incorporates two modes of 8-bit parallel READ/WRITE, as well as additional functions for test-time reduction. Eight 1-Mb family members can be produced by metal mask selection. The device uses static column circuitry along with two-stage intermediate output buffers to achieve a typical column address access time of 20 ns.