Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task

Continuing technological advances in single-chip intelligence and storage cell density, and in bulk store performance provide increasing opportunities to construct multiple microprocessor systems. The objective of this experimental study was to explore the performance of selected system architectures in a manner sufficiently detailed, quantitative and realistic to 1) contribute to our understanding of the fundamental behavior of such systems and 2) permit practical designs to follow from the results. Four different classes of system architecture were studied: System I-fully connected; System II-bused with private primary store; System III-bused with both public and private primary store; and System IV-a uniprocessor system. All multiple-processor configurations comprised autonomous computing units which were loosely coupled with parallel links, and performed dedicated functions in a cooperative tasking environment. At the time the study began much of the anticipated technology was not yet available so detailed deterministic models of the systems were developed. All testing was done using a specially developed discrete simulation tool called the System-State Model (SSM). Both hardware and software details, derived from an operational system, were included in each model structure to represent the necessary concurrent, hierarchical, and ranked activity. A basic, interactive data base task was used as the test case. Experimental parameters included number of users, task load, console channel and bulk store channel configurations, and secondary store access time regimes. Over one hundred simulation runs were made which provided both internal and external performance measurements. Analysis of the results revealed a complex set of performance relationships which, in turn, led to several fundamental assessments. These include 1) every configuration can have its performance severely limited by the presence of any one of several key factors, 2) bulk store access time regimes and channel configuration have a critical effect on all system architectures, 3) performance distinctions among systems become more pronounced with increased number of users and with task load, and 4) each of Systems II, III, and IV manifests unique and useful performance characteristics and could be the configuration of choice under the right conditions. Overall, the results provide detailed confirmation of the utility of such systems and suggest a variety of specific tradeoffs among the architectures.