Correlation of fabrication process and electrical device parameter variations

A program for modelling IC fabrication processes is described. Simulated and measured impurity profiles are shown for a bipolar transistor technology. These profiles are used to study the sensitivity of electrical device parameters to process variations. A comparison of simulated device performance using process models gives parameters which bracket measured results for 35 die across a wafer. A statistical model is given which relates twelve parameters to the base transport current.