Schottky collector I/sup 2/L

A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described.