An assessment of VLSI and embedded software implementations for Reed-Solomon decoders

This paper examines Reed-Solomon time-domain and frequency-domain decoder implementations in both software and hardware. The focus was on designing area-efficient, low-power and low-complexity decoders suitable for today's moderate data-rate applications. Two decoder chips were designed using a synthesized standard cell library in a 0.18 /spl mu/m CMOS process, targeting a 160 Mbps decoding rate. The time-domain decoder was fabricated with a core area of 1.50 mm/sup 2/.