Low-power turbo equalizer architecture

In this paper, we propose a low complexity architecture for turbo equalizers. Turbo equalizers jointly equalize and decode the received signal by exchanging soft information iteratively. The proposed architecture employs early termination of the iterative process when it does not impact the bit-error rate (BER). Early termination enables the powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that the complexity is reduced by 20% /spl sim/ 59% and 8% /spl sim/ 58% in equalization and decoding, respectively. In addition, the number of iterations is reduced by 30% /spl sim/ 47% with negligible degradation in BER.