Extremely scaled fully depleted SOI CMOS

There is new interest in FD/SOI CMOS because of its potential superior scalability relative to bulk-Si CMOS. Indeed, recent experimental device studies have implied that short-channel effects (SCEs) can be controlled in FD/SOI MOSFETs scaled to L/sub gate/ < 50nm by thinning the SOI-film thickness (t/sub Si/). While series resistance in such scaled devices has been stressed as a significant issue, simultaneous threshold-voltage (V/sub t/) control in both CMOS devices, dependent on gate work functions as well as t/sub Si/ and Si-channel doping density (N/sub CH/), on carrier-energy quantization in thin Si films, and on the SCEs, has not been addressed comprehensively. In this paper, we use numerical device simulations and process-based device circuit simulations to examine this issue, giving insights on FD/SOI CMOS scalability and performance.