A logic-process-compatible SOI DRAM gain cell operating at 0.5 volt

A novel SOI DRAM gain cell operating at 0.5 V is proposed. It consists of a p-channel JFET and an n-channel MOSFET, whose source diffusion functions as gate diffusion of the JFET as well. Signal charge is stored in the gate diffusion capacitance of the JFET, leading to the modulation in its source-drain conductance. Mixed-mode simulation with the use of a device simulator reveals that the proposed SOI DRAM gain cell is able to operate properly under supply voltage as low as 0.5 V.