Establishing advanced implant annealing for the 65 nm technology node

An essential requirement for the continued scaling of CMOS technology is the ability to fabricate junctions with decreased depth and increased abruptness without compromising the maximum activation level of dopants. Reduction of ion implantation energy has been instrumental in meeting this requirement and will play an important role in the future. However, advances in annealing technology continue to be critical in order to realize the potential benefits of lower energy implants. Spike anneals, in which the wafer only spends 1 to 2 s within 50/spl deg/C of the peak temperature, are playing a key role in 130 nm and 90 nm node technologies. These anneals have proved successful in mitigating enhanced diffusion effects. They have enabled superior junctions by allowing annealing at higher temperatures to increase electrical activation while limiting diffusion by virtue of sharper temperature-time profiles. Employing temperature-time profiles of greatly increased sharpness can extend this principle further. We have used a flash-lamp based system to investigate the evolution of dopant profiles and the associated damage structure following low-energy ion implantation. Peak temperatures of values up to 1300/spl deg/C were used while the sharpness of the temperature-time profile was sharpened in to the sub-millisecond range. Profiles with significantly reduced junction depths have been obtained without compromising high active concentration. This method has the potential to produce profiles with improved abruptness but we show that this is sensitive to the choice of implantation conditions. Under optimized conditions it is now possible to take full advantage of reducing implantation energy and produce profiles that can be expected to enable device technology at the 65 nm node and beyond.