Calibration of parallel /spl Delta//spl Sigma/ ADCs

A method of calibrating the gain and offset of each channel in parallel /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) is presented. It uses a digital /spl Delta//spl Sigma/ modulator to perform fast and simple offline calibration. Simulations performed on the converter show greater than 30-dB reduction in unwanted tones when this calibration algorithm is used on an eight-channel second-order time-interleaved parallel converter with a 1% gain mismatch and 1-mV offset mismatch. The calibration method is general and can be used with any parallel /spl Delta//spl Sigma/ ADC including time-interleaved- and Hadamard-modulation-based architectures.