Test-bed board for 16/spl times/64 stereo vision CNN chip

The implementation of an artificial vision algorithm in real time is really attractive in such an application as the field of environment sensing. The SVCNN (stereo vision cellular neural network) chip is an analogue circuit able to compute in real time the Disparity Map from a couple of images by using a stereo visual system algorithm. A "test-bed" board for the 16/spl times/64 SVCNN chip is presented in this paper. This board is composed of an analogue processing core implemented by two 16/spl times/64 SVCNN chips together with a digital high performance pre-processing unit and a video grabbing section.