A CMOS low-IF programmable gain amplifier with speed-enhanced DC offset cancellation

This paper presents a programmable gain amplifier (PGA) for a dual band (GSM900/DCS1800) low-IF receiver. It uses a negative feedback approach to achieve the high linearity requirement. In addition to the amplifier, anti-alias filtering and DC offset removal are included for the subsequent IF signal processing. A dual-bandwidth algorithm is developed to speed up the settling time on DC removal. A modified Sallen-Key filter helps to provide better than 40 dB anti-aliasing and blocker attenuation near the sampling frequency of 13 MHz. The overall PGA gain varies from 0 dB to 46 dB with 2 dB per step. With a 0.25 /spl mu/m CMOS process, this device dissipates 10.3 mW from a 2.7 V supply voltage.