Race-free clocking of CMOS pipelines using a single global clock

A novel, single-phase, race-free CMOS circuit clocking technique, which provides and uses complementary logic, is presented. The clock can be driven by a sinusoidal waveform. This avoids any requirement for transmitting the very-high-frequency components associated with fast clock edges. Such circuits are therefore less sensitive to clock distortion caused by transmission-line effects.<
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