A 1.2 V 10-b 100-MSamples/s A/D converter in 0.12/spl mu/m CMOS

A CMOS analog-to-digital converter (ADC) utilizing folding, averaging and distributed interpolation is described. Fabricated in a digital 0.12 /spl mu/m CMOS process, the ADC occupies 0.32 mm/sup 2/ while dissipating 140 mW from a single 1.2 V supply. The experimental results show that the converter achieves 55dB SNR at sampling frequencies up to 100MHz.