High-speed data transmission using low-frequency clocks

An architecture for parallel-to-serial conversion that avoids high-frequency clocking is introduced. Instead of using fast clocks, it requires precise relative timing throughout the circuit. Such an approach is natural for an integrated circuit, where clock distribution is difficult, but devices in close proximity are very well matched. Roughly speaking, the architecture requires that the data be appropriately recorded, skewed with low-frequency clocks having precise phase mismatches, and merged through a combinational logic network with carefully matched delays. Both theory and implementation are discussed, although the approach is not closely tied to a specific technology.<
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