A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, and measures 6.3 mm*4.8 mm. A basic gate delay of 40 ps has been achieved. A 16*16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W.<
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