Power dissipation estimate by switch level simulation (CMOS circuits)

A method for calculating power dissipation of digital CMOS circuits is presented. The estimate is made during switch-level simulation and is thus based on the simulated activity in the circuit. Dissipation from dynamic switching, the short-circuit component, and static currents are considered. The average power dissipation is overestimated by as little as 5-10% compared to SPICE results, if X-states and spikes can be avoided during the simulation.<
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