An evaluation of memory management schemes for a multimemory-multiprocessor system

The virtual memory management schemes for a multimemory-multiprocessor system based on bus-structured architecture are dealt with. The design issues peculiar to such a system are pointed out. Various schemes to manage them are introduced. Simulations of the memory management schemes are carried out to evaluate the design alternatives. A queuing network model is established to predict the overall system throughput under various paging system policies. From these experiments, the authors observe the behavior of their memory system, which may provide clues for future improvement.<
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