A multifunctional processing board for the fast track trigger of the H1 experiment

The electron-proton collider HERA is being upgraded to provide higher luminosity from the end of the year 2001. In order to enhance the selectivity on exclusive processes a fast track trigger (FTT) with high momentum resolution is being built for the H1 collaboration. The FTT will perform a three-dimensional (3-D) reconstruction of curved tracks in a magnetic field of 1.1 Tesla down to 100 MeV in transverse momentum. It is able to reconstruct up to 48 tracks within 23 /spl mu/s in a high track multiplicity environment. The FIT consists of two hardware levels L1, L2 and a third software level. Analog signals of 450 wires are digitized at the first-level stage followed by a quick lookup of valid track segment patterns. For the main processing tasks at the second level such as linking, fitting, and deciding, a multifunctional processing board has been developed by the ETH Zu/spl uml/rich, Switzerland, in collaboration with Supercomputing Systems, Zu/spl uml/rich. It integrates a high-density field programmable gate array (FPGA) and four floating point digital signal processors (DSPs). This presentation will mainly concentrate on second trigger level hardware aspects and on the implementation of the algorithms used for linking and fitting. Emphasis is especially put on the integrated content addressable memory (CAM) functionality of the FPGA, which is ideally suited for implementing fast search tasks like track segment linking.