Electrical stressing-induced degradation effects in solid phase crystallized polysilicon thin film transistors

The degradation of the electrical parameters of unhydrogenated SPC polycrystalline silicon TFTs subjected to stressing gate and drain biases was investigated. When V/sub GS/ stressing alone is applied the threshold voltage V/sub th/ shows an initial negative shift, attributed to hole trapping, and then a turnaround to a positive shift with a logarithmic stressing time dependence which occurs sooner for larger stressing VGS. The latter shift is attributed to electron trapping in stress-induced states in the oxide and at the polysilicon/SiO/sub 2/ interface. The subthreshold swing, the total midgap trap state density and the transconductance also exhibit logarithmic degradation, attributed to a stress-induced acceptor trap creation at the interface and in the polysilicon active layer; this is consistent with the electron trapping process inferred from the V/sub th/ shift. A small V/sub DS/ stressing applied in combination with V/sub GS/ stressing was found to suppress this V/sub th/ turnaround effect and enhance the degradation of all parameters.