Abstract:
This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units. These compressors are building blocks for binary multipliers. Various...Show MoreMetadata
Abstract:
This paper explores various low power higher order compressors such as 4-2 and 5-2 compressor units. These compressors are building blocks for binary multipliers. Various circuit architectures for 4-2 compressors are compared with respect to their delay and power consumption. The different circuits are simulated using HSPICE. A new circuit for a 5-2 compressor is then presented which is 12% faster and consumes 37% less power.
Published in: Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)
Date of Conference: 04-07 November 2001
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7147-X
Print ISSN: 1058-6393