A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme

An equalizing transceiver was implemented by using a 0.35-/spl mu/m CMOS technology for DRAM bus system. An equalization scheme was used in the receiver to reduce intersymbol interference (ISI). To maximize the data rate, a one-to-eight demultiplexing scheme was used in the equalizer of the receiver such that eight equalizers operate in parallel at the clock frequency, which is one-eighth the data rate. The maximum data rates were measured to be 840 Mb/s with twelve 5-pF capacitors connected in uniform spacing along a transmission line. The test criterion for successive transmission was set to the bit-error rate (BER) of 10/sup -12/ for the pseudorandom binary sequence (PRBS) data. The effectiveness of equalizers was demonstrated by measuring the BER with equalizers on and off, respectively. The chip size was 800/spl times/400 /spl mu/m/sup 2/ and the supply voltage was 3.3 V.