Effects of backend processing on counter-doped n/sup +/ poly-Si resistance

The effects of thermal and implant processing on phosphine-doped n/sup +/ polysilicon are investigated. These effects include growth of an analog capacitor dielectric, pre- and post-S/D implant conditions and ambients, P/sup +/ implant species, and double-level metal processing. In particular, the effects on counter-doped polysilicon are investigated. Both elemental and electrical analysis were performed to characterize these effects. By minimizing post-metal heat treatment, and protecting the polysilicon from excessive boron incorporation, low-resistance contacts can be made to counter-doped n/sup +/ poly.<
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