A pipeline of associative memory boards for track finding

We present a pipeline of associative memory boards for track finding, which satisfies the requirements of level two triggers of the next LHC experiments. With respect to previous realizations, the pipelined architecture warrants full scalability of the memory bank, increased bandwidth (by one order of magnitude), increased number of detector layers (by a factor 2). Each associative memory board consists of four smaller boards, each containing 32 programmable associative memory chips, implemented with low-cost commercial FPGA. FPGA programming has been optimized for maximum efficiency in terms of pattern density and PCB design has been optimized in terms of modularity and FPGA chip density. A complete AM board has been successfully tested at 40 MHz, and can contain 6.6/spl times/10/sup 3/ particle trajectories.