A low-power 10 bit ADC in a 0.25 /spl mu/m CMOS: design considerations and test results

This paper presents the design and test of a low power analog to digital converter implemented in a commercial 0.25 /spl mu/m CMOS technology. The circuit has been developed to serve as a building block in multi-channel data acquisition systems for high energy physics (HEP) applications. Therefore medium resolution (10 bits), very low power consumption and high modularity are the key features of the design. In HEP experiments the resistance of the electronics to the ionizing radiation is often a primary issue. Hence the ADC has been laid-out using a radiation tolerant approach. The test results show that the chip operates as a full 10 bit converter up to a clock frequency of 30 MHz. No degradation in performance has been measured after a total dose of 10 Mrd (SiO/sub 2/).