Offset in CMOS magnetotransistors. I. Analysis of causes

Fabrication imperfections cause offset in CMOS magnetotransistors (MTs). In this paper, MT offset is experimentally characterized and its causes are analyzed for two different commercial CMOS processes. For the MT structures chosen as references, the average absolute value of the offset in terms of a relative imbalance of two collector currents is up to 2.7%. The mean offset temperature drift between -40/spl deg/C and +140/spl deg/C is 0.25%. The offset exhibits a high degree of variation on a very small spatial scale. Additionally, variations on a large scale over the wafer are observed and, in some cases, systematic influences. The actual offset contributions of the various identified possible sources are investigated. Misalignment of the metal contact mask occurring during photolithography dominates large scale offset variations and can also have a systematic component. Another systematic influence arises from nonorthogonal dopant implantation. Doping inhomogeneities are a dominating contribution to local variations as indirect evidence suggests. Further, mismatch in emitter-collector spacing is critical. Suppressed sidewall injection magnetotransistors (SSIMTs) showing an enhanced sensitivity exhibit a quadrupling of the offset, which comes from a misalignment of the emitter guard ring. The obtained results are the basis for dedicated offset reduction in MTs as well as the development of MT-like test structures for processing tolerances.