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Uniprocessor virtual memory without TLBs | IEEE Journals & Magazine | IEEE Xplore

Uniprocessor virtual memory without TLBs


Abstract:

We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead mana...Show More

Abstract:

We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features as shared memory, superpages, fine-grained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardware-defined mechanisms.
Published in: IEEE Transactions on Computers ( Volume: 50, Issue: 5, May 2001)
Page(s): 482 - 499
Date of Publication: 07 August 2002

ISSN Information:


1 Introduction

Changing trends in technologies, notably cheaper and faster memory hierarchies, have made it worthwhile to revisit many hardware-oriented design decisions made in previous decades. Hardware-oriented designs, in which one uses special-purpose hardware to perform some dedicated function, are a response to the high cost of executing instructions out of memory; when caches are expensive, slow, and/or in scarce supply, it is a perfectly reasonable reaction to build hardware state machines that do not compete with user applications for cache space and do not rely on the performance of the caches. In contrast, when the caches are large enough to withstand competition between the application and operating system, the cost of executing operating system functions out of the memory subsystem decreases significantly, and software-oriented designs become viable. Software-oriented designs, in which one dispenses with special-purpose hardware and instead performs the same function entirely in software, can offer increased flexibility over hardware state machines at a modest cost in performance. One current example is the translation of x86 instructions by Transmeta's code-morphing software layer [11]; this performs the same type of function as the front-end of the Pentium Pro/II/III pipeline, which turns x86 instructions into RISC-like uops in hardware [16].

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