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Uniprocessor virtual memory without TLBs | IEEE Journals & Magazine | IEEE Xplore

Uniprocessor virtual memory without TLBs


Abstract:

We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead mana...Show More

Abstract:

We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features as shared memory, superpages, fine-grained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardware-defined mechanisms.
Published in: IEEE Transactions on Computers ( Volume: 50, Issue: 5, May 2001)
Page(s): 482 - 499
Date of Publication: 07 August 2002

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