Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test

Static Random Access Memories (SRAMs) often occupy a significant area of contemporary Systems on Chip (SoC) integrated circuits (ICs) and therefore determine their energy consumption, yield, and reliability. The sense amplifier (SA) is a critical SRAM circuit that requires careful design. The offset in the SA does not scale well with technology scaling and has become an impediment to realizing energy efficient SRAMs. Additionally, the offset in SAs can also give rise to intermittent failures (soft-failures) in SRAMs that are difficult to detect through traditional march test algorithms.This tutorial is divided into two parts. The first part focuses on SA design and contrasts techniques for mitigating SA offset voltage. The second part addresses SRAM design and test considerations for the SA offset voltage. Traditional approaches of SRAM testing are inadequate to cover SA offset related failures, and we highlight algorithmic and Design for Testability (DfT) techniques for detecting such failures. The tutorial draws data from several different publications, as well as from several test chips designed by the presenter and his graduate students.