The Development and Production of the ADDC for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

A series of upgrades will be implemented in the Large Hadron Collider (LHC) to allow luminosity increases in next ten years. The ATLAS experiment will also follow the similar upgrade steps. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micromegas detector of the ATLAS New Small Wheel (NSW) upgrade. The Address in Real Time (ART) signals are generated by the front-end ASIC, named VMM chip, to indicate the address of the first above-threshold event which is used to generate the trigger decision. An ART ASIC is custom designed to receive the ART signals from the VMM chips and do the hit-selection processing. Processed data from ART ASIC will be transmitted out of the NSW detector to trigger processor through GBTx serializer, VTTx optical transmitter module and fiber optical links.The ART signal is critical for the ATLAS experiment trigger selection thus the functionality and stability of the ADDC is very important. After development and evaluation of four versions of prototype, the production of ADDC has been launched. 600 pieces of ADDCs will be assembled and tested with the automated test platform which includes a Xilinx VC707 FPGA development kit, a custom designed FMC mezzanine board and related firmware and software. With this test platform, all the functionalities and long-term stability of ADDC can be verified without other electronics of the NSW. This paper will introduce the ADDC prototype development, ART ASIC production packaging, ADDC production test procedure and test results.