A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC

This paper presents a successive-approximation-register (SAR)-assisted time-interleaved digital-slope analog-to-digital converter (ADC), which takes advantage of both moderate conversion speed of the SAR ADC and low noise of the digital-slope ADC. A coarse SAR ADC is pipelined with 4 channels of digital-slope fine ADC through passive residue transfer for speed, precision and power optimization. A charge sharing-based implementation of the digital-slope ADC eliminates the need for power-consuming on-chip reference buffers. A compact bootstrapped switch-based chopper is proposed to minimize the hardware overhead. Designed and simulated in a 28 nm FDSOI CMOS technology, the proposed ADC achieves a SNDR of 63.74 dB at 500 MS/s while dissipating 2.4 mW, leading to a FOM of 3.83 fJ/conv.-step.