Modeling of Capacitive Coupled Interconnects for Crosstalk Analysis in High Speed VLSI Circuits

In this paper, we estimated the crosstalk noise for CMOS driver with capacitive coupled interconnect model in High-speed digital VLSI circuits. Crosstalk noise is one of the essential parameters for designing accurate interconnect models. As monotonically increasing of clock frequencies, circuit density and decreasing of rise time, degrading the circuit performance. The design of L - Model Interconnect with capacitively coupled at high frequencies, estimated the crosstalk noise on victim lines on both ends with respect to aggressor line for global interconnects at 180nm Technology Node. And also carried out the analytical and simulated results in Advanced Design System (ADS) and validated with SPICE tool.