Spurious-Free Synthesizer Design for Fast Frequency Hopping Spread Spectrum

A spurious-free synthesizer design for Fast Frequency Hopping Spread Spectrum (FFHSS) is presented in this paper. By the proposed method, a hardware is designed and this hardware is both applicable for frequency hopping receivers and transmitters which operates at L-band frequency. All the simulations and tests are conducted within the frequency range of 880 MHz to 1330 MHz. Proposed design allows very small frequency tuning step size as low as 3 Hz due to fractional Phase Lock Loop (PLL). In this work, we propose a method to mitigate in-band spurs for FFHSS by optimizing reference clock frequency. By using this method, the power of spurious signals is reduced up to 40 dB for FFHSS. Different clock reference frequencies, required by Radio Frequency (RF) PLL's are ensured by using a clock distributor. Proposed design is suitable for FFHS systems with a guard time more than 200 us.