A Temperature-Compensated LC-VCO PLL and a Power-Efficient Decision Feedback Equalizer for Multi-Standard Serial Links

This paper presents a temperature-compensated wideband LC-VCO phase-locked loop (PLL) and a power-efficient decision feedback equalizer (DFE) for multi-standard serial link applications. The PLL adopts a new temperature compensation scheme to reduce the LC-VCO temperature frequency drift without sacrificing frequency tuning range. The DFE utilizes a half-rate speculative architecture with a non-50% duty cycle clocking scheme, achieving 20% faster speed compared with the conventional solutions. Designed in a 130 nm CMOS technology, the PLL achieves a 5.6GHz to 13.4GHz tuning range by using two VCO cores while remaining locked from -40°C to 85°C. At 25°C, the PLL has a random jitter (RJ
_rms
) of 0.37pS at 11.44GHz and consumes 50.88mW of power. Designed in a digital 65nm CMOS process, the DFE operates up to 21Gb/s over a 25dB loss channel, consuming 20.8mW of power.