Optimization techniques for maximum power-efficiency of deep sub-micron CMOS digital circuits

This paper presents results of a study to locate the optimal operating power supply voltage for a maximum power-efficiency operation of CMOS digital circuits in a deep sub-micron environment. The results show that the optimal V/sub DD/ is a strong function of NMOS and PMOS device threshold voltages and their sizes. Depending on the capacitive loading, the optimal V/sub DD/=/spl xi/(|V/sub tp/|+V/sub tn/), where /spl xi/ is (0.9-1.1). The study targets low-power low-voltage applications of digital pass-transistor circuits with multiple operating voltages. The analysis has been performed using BSIM Level 28 models and verified with HSPICE. The experimental circuits were designed in 0.35 /spl mu/m CMOS technology.