Integration of SPAD in 28nm FDSOI CMOS technology

This paper reports the first experimental results obtained on a Single Photon Avalanche Diode (SPAD) implemented, in a 28nm FDSOI CMOS technology. The main originality relies on the integration of the SPAD below the buried oxide with the logic on-top in the thin silicon layer, providing an intrinsic 3D stack. The expected benefits are a much higher fill factor with embedded high performance and low power electronics. A test-chip has been fabricated with the commercial STMicroelectronics CMOS28FDSOI technology without any design rule violation nor process customization. SPAD breakdown has been investigated with electroluminescence cartography and breakdown voltage measurements. Afterwards, first dark count rate measurements are reported according to temperature and excess bias. To our knowledge, it is the first demonstration of SPAD devices in a FDSOI CMOS technology. Based on these encouraging results, the study will be pursued for more statistical data acquisition and for SPAD characterization under illumination.