A dead time free high-speed data acquisition architecture

Abstract an innovative data acquisition architecture, allowing the virtual elimination of dead-time in most experimental setups, is presented. The proposed architecture keeps a balanced equilibrium between complexity, speed, data storage memory, and cost, the approach taken in its design re-enforces modularity and hardwares block reuse, in a line with strong links to object-oriented programming design techniques. The architecture is optimised for high-speed data acquisition (in the range of hundreds MSPS). The elected architecture surfaced from a study of several significant modern architectures and from experience acquired while developing an object-oriented approach for a previously developed high-speed architecture. This process of software development leads naturally to a concept where a clean separation between data transfer, and control and trigger signals, suggested a similar general decomposition of the data acquisition hardware, in such a way that the same fundamental hardware blocks can be used in several different configurations. Two different implementations of the architecture being developed are presented, one using the MAX104, a 1 GSPS, 8-bit ADC from MAXIM, the other a lower speed 12 bit, 65 MSPS ADC (AD6640). Their basic communality is the data storage block, organized as a 16-bit wide circular memory of over 12 MBytes that can be continuously and simultaneously written and read at 100 MHz. If the trigger signal can be generated within tenths of ms, and if the data can be read out before re-writing occurs, then the system will show no dead time. It is expected that such data acquisition architecture could be useful in experiments ranging from plasma physics, where long discharges are foreseen, and high energy physics, where on-line high data reduction rates is a must.