MATRIX: A novel two-dimensional resistive interpolation 15 ps time-to-digital converter ASIC

This paper presents a 4-channel TDC chip demonstrator with the following features: 15-ps bin width, 1280 ns dynamic range, dead time <; 20 ns, up to 10 MHz of sustained input rate per channel, around 45 mW of power consumption and very low area in a 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry which is based on a resistive interpolation mesh circuit (patented), a two-dimensional regular structure with outstanding performance in terms of power consumption, area and low process variability.