RSVP: Soft Error Resilient Power Savings at Near-Threshold Voltage Using Register Vulnerability

With the ever-growing scaling of computing capability, computing systems like supercomputers and embedded systems are bounded by limited power nowadays. Upon the mutually constrained nature between power efficiency and resilience, trade-offs of them have been extensively studied for achieving the optimal performance-power ratio, either under a certain power cap, or within the requirement of quality metrics of applications. Theoretically, running programs in the low-power mode of computational components (e.g., CPU/GPU) can lead to increasing on-chip failure rates in terms of register-level susceptibility to soft errors. However, experimentally, such errors may not arise due to register vulnerability - errors occur at non-vulnerable register access intervals are invalidated and thus will not propagate to later execution. In this work, leveraging register vulnerability, we investigate the validity of failure rates in computing systems at Near-Threshold Voltage (NTV), and empirically evaluate the practice of achieving optimal power savings without incurring observable number of soft errors during program runs. We propose the framework of RegiSter Vulnerability based Power efficiency (RSVP) for reliable and power efficient computing. Experimental results for a wide spectrum of applications on a power-aware simulated platform demonstrate the power saving capability of RSVP, by 11.2% on average, without incurring runtime soft errors at the optimal NTV level for power savings.