High speed low power wireless signal timing analysis on FPGA using turbo coding and Viterbi algorithm

As higher and higher speeds are used in wireless appliance, error correction continues to pose a considerable design challenge. Turbo codes exhibit attainment, in terms of bit error probability, that is very close to the Shannon limit and can be efficiently achieved for high-speed use. Turbo encoders and decoders have been introduced, most of which are based on convolution encoding. Here each encoder produces a single check bit for each input bit and that input bit is preserved. In the earlier convolution encoders the input bit is not preserved. In turbo coding the dynamic variation changes in convolution codes is familiar as recursive systematic convolution codes (RSC).