Reconfigurable array-based design for flexible cryptography chip architecture

In this paper, we present an area efficient crypto chip for sharing and selecting the hardware operation of the one public-key cipher and three block ciphers (ECC, AES, ARIA, and HIGHT) and reconfigurable crypto chip of an array-processor-based cryptography algorithm. Based on the proposed processor, we designed an encryption chip that reduced the total area of ECC, AES, ARIA and HIGHT by 21% using 0.18μm CMOS technology. Also, Cryptography Array Processor (CAP) of ECC, AES, ARIA, and HIGHT indicates high performance at 40Kbps, 1,085 Mbps, 746 Mbps and 175 Mbps respectively. The proposed design of crypto chip shows the reconfigurable flexibility of the encryption algorithm and high hardware performance.