Preventing Reverse Engineering using threshold voltage defined multi-input camouflaged gates

Semiconductor devices are increasingly getting more vulnerable to counterfeiting due to Reverse Engineering (RE) of Intellectual Property (IP). Securing the IPs from counterfeiting is an important goal towards trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an adversary from de-layering the chip and stealing IP. Among other techniques, threshold voltage modulation has been proposed to realize 2-input camouflaging logic in both static and dynamic logic gate families. Since threshold voltages are asserted during fabrication and are difficult to identify during RE, the adversary will be forced to launch brute-force search. In this paper, we extend the concept of threshold-voltage defined logic to design 3-input static camouflaged gates capable of performing six Boolean functions (NAND, NOR, AOI, OAI, XOR, XNOR). Simulation results show an average of 3.03× delay overhead and 12.33× power overhead compared to standard CMOS gates. A methodology to design multi-input camouflaged gate is also proposed using a similar technique. Finally, we perform a threat analysis on the camouflaged gate to assess the security and integrity of the design by identifying temperature sensitivity and power signature as potential side channels.