Influence of passivation anneal position on metal coverage dependent mismatch and hot carrier reliability

Prolonged higher temperature passivation anneals are purported to minimise metal coverage induced transistor mismatch in multi-level-metal (MLM) CMOS circuits. However, process changes that improve unstressed (T=O) device matching do not necessarily lead to better matching under hot carrier stress. As a result, matched transistor parameters can drift disproportionately during circuit operation and increase mismatch. Here, we demonstrate that the popular method of improving mismatch by increasing the post-cap final passivation anneal temperature and time can adversely impact the DC hot carrier ageing (HCA) behaviour. By changing the position of the passivation anneal in the fabrication process flow, the device is made more robust to hot carrier ageing while improving transistor matching.